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Home > Products > IP Licensing |
 Since 1993, Tvia has developed many key technologies in video signal processing. These technologies are now offered for licensing as IP blocks; with a partial list given below. Please contact iplicensing@tvia.com for further discussion
AFE (Analog Front End) or ADC The AFE is a five channel, complete 9-bit, 160 MSPS, monolithic analog interface optimized for capturing RGB graphics and video signals from personal computers and workstations. It includes five 9-bits 160 MHz ADC with internal 1.25 V reference, three 3-bits ADC, PLL, and programmable gain, offset, and clamp control.
LVDS transmitter LVDS transmitter converts 35 bits of LVCMOS/LVTTL data into five LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a sixth LVDS link every cycle of the transmit clock 35 bits of input data are sampled and transmitted. At a transmit clock frequency of 85 MHz, 18/24/30 bits of RGB data and 3 bits of LCD timing and control data (HDE, HS, VS) are transmitted. Support interleave transmit
Video DAC Tvia Video DAC is a triple high speed, digital-to-analog converter IP. It consists of three high speed, 8-bit video DACs with complementary outputs, a standard TTL input interface, and a high impedance, analog output current source.
PLL PLL (phase locked loop) is a closed-loop frequency-control system based on the phase difference between the input clock signal and the feedback clock signal of a controlled oscillator.
The main block are the phase frequency detector (PFD), loop filter, voltage controlled oscillator (VCO), and counters. Its input frequency can be between 5MHZ and 50MHZ, the output frequency can up to 200MHZ. The VCO frequency can be 800MHZ~1.2GHZ.
2D Graphic Engine TVIA 2D Coprocessor is part of GPU processor. TVIA 2D accelerator (64bit engine) supports 8/16bpp Rop2 ------ Color Fill, Pixel Blt, Pattern Blt, Turbo mono Blt, and transparent Blt.
TV Encoder The TV Encoder IP incorporates a proprietary flicker-free technology and an integrated NTSC/PAL TV encoder for true TV quality. The IP provides the output to TV connectors, including NTSC/PAL S-video, NTSC/PAL composite, SCART/RGB and 16:9 wide-screen TV. It can be a widely used in PC-TV systems.
LCD panel pre-processor Adaptive back light control The Adaptive BLC (Back Light Control) is used to enhance the dynamic contrast by changing the LCD Backlight. The Adaptive BLC generate Back Light gain base on the input source to control LCD Backlight.
Frame Response Accelerator The FRA (Frame Response Accelerator) gives a way to accelerate the Frame Response for LCD panel, and it is also know as Overdrive Engine.
Frame Rate Control Dithering
The FRC is designed for increasing display panel’s native color levels by frame pixel on/off rate control to met different panel interface. At the same time it applies special arithmetic to avoid flicker noise. It supports 10bit input and 8bit/6bit/4bit output formats.
Video Processor DCCE Dynamic eliminate composite input cross color noise when Y input at high frequency. The DCCE (dynamic cross color elimination) also have an option to do YRCV(Y recovery).
DCM The DCM (Digital Color Management) module uses an internal three-dimensional LUT (Look Up Table) to re-map the input YUV data. This re-mapping of the YUV data may be done for calibrating the YUV data for a particular LCD panel, or for special color management.
ACC Adaptive Contrast Control is integrated with processing on Y signal for enhancing the video contrast in one frame automatically.
Motion-adaptive de-interlace Motion-adaptive de-interlace provides temporal motion-adaptive de-interlace with 4-field (2-frame) data. It includes film mode (32pulldown and 22pulldown) detection and adaptation, still mode detection and adaptation. And it also provides CUE/ICP detection and correction.
Sharpness Sharpness Enhancement IP blocks can adjust video image data on both horizontal and vertical direction with programmable coefficient.
Alpha Blending Alpha Blending IP module can merge 3 layers video image into one. The blending coefficient can be programmable according to the application.
Color enhancement Color enhancement provides 3 primary color enhancements, skin tone correction and Blue stretch function.
Scaling engine Scaling engine provide up or down scaling with video image to fit the different output resolutions or panel size.
Gamma Correction With a programmable LUT (look-up-table) and a auto measure software, the Gamma correction function can easily used for panel drive application.
Clock Processor Clock recovery Clock Recovery IP uses the external Horizontal Sync to restore the original Pixel clock.
DLL DLL (Delay Locked Loop) IP provide 4 set of locked timing delay to synchronize with the input clock for DDR memory usages.
Phase adjustment PA (Phase adjustment) is a programmable delay circuit for phase adjustment which provide a 5-bits register for programming.
Duty Cycle Correction DCC(Duty Cycle Correction)IP can fix the input clock duty cycle to 50%±2%。
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